VHDL Code For D-FF Behavioral Model

VHDL Code For D-FF Behavioral Model

 

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity dffbeh is

Port ( d,clk : in  STD_LOGIC;

q,qb : inout STD_LOGIC);

end dffbeh;

architecture dffbehar of dffbeh is

begin

process(d,clk)

begin

if(clk’event and clk=’1′) then q<=d; qb<=not d;

end if;

end process;

end dffbehar;