Verilog Code for D-FF Behavioral level:
module dffbeh(d,clk,rst,q);
input d,clk,rst;
output q;
reg q;
always @ (posedge clk)
if (rst)
q <= 1’b0;
else
q <= d;
endmodule
Tag Archives: flip flop
Verilog Code for T-FF Behavioral level
Verilog Code for T-FF Behavioral level:
module tffbeh (t,clk,rst,q);
input t,clk,rst;
output q;
reg q;
always @ (posedge clk)
if (rst)
q <= 1’b0;
else
q <= !t;
endmodule
Verilog Code for JK-FF Gate level
Verilog Code for JK-FF Gate level:
module jkffgl(j,k,clk,cl,q,qb);
input j,k,clk;
input cl;
output
q,qb;
wire j1,k1,q1,qb1,j2,k2,q2,qb2,clk2;
not n(clk2,clk);
nand n1(j1,j,clk,qb2,cl);
nand n2(k1,k,clk,q2);
nand n3(q1,j1,qb1);
nand n4(qb1,k1,q1);
nand n5(j2,q1,clk2);
nand n6(k2,qb1,clk2);
nand n7(q2,j2,qb2);
nand n8(qb2,k2,q2,cl);
assign q=q2;
assign qb=qb2;
endmodule
Verilog Code for SR-FF Behavioral level
Verilog Code for SR-FF Behavioral level:
module srffbeh(s,r,clk,q,qb);
input s,r,clk;
output q,qb;
reg q,qb;
always @ (s or r or clk)
case({s,r})
2’b01 : begin q=0; qb=1; end
2’b00 : begin q=0; qb=1; end
2’b10 : begin q=1; qb=0; end
2’b00 : begin q=1; qb=0; end
2’b11 : begin q=1’bz; qb=1’bz; end
endcase
endmodule
Verilog Code for SR-FF Data flow level
Verilog Code for SR-FF Data flow level:
module srffdf(s,r,clk,q,qb);
input s,r,clk;
inout q,qb;
wire s1,r1;
assign s1=!(s & clk);
assign r1=!(r&clk);
assign q=!(s1&qb);
assign qb=!(r1&q);
endmodule
Verilog Code for SR-FF Gate level
Verilog Code for SR-FF Gate level:
module srffgl(s,r,clk,q,qb);
input s,r,clk;
inout q,qb;
wire s1,r1;
nand n1(s1,s,clk);
nand n2(r1,r,clk);
nand n3(q,s1,qb);
nand n4(qb,r1,q);
endmodule
VHDL Code For T-FF
VHDL Code For T-FF
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity tff is
port ( t,clk : in std_logic;
q: out std_logic);
end tff;
architecture tffarc of tff is
begin
process(t,clk)
begin
if(clk’event and clk=’1′) then
q<= not t;
end if;
end process;
end tffarc;
VHDL Code For JK-FF
VHDL Code For JK-FF
library ieee;
use ieee.std_logic_1164.all;
entity jkffbeh is
port(cp,j,k: in std_logic;
q: buffer std_logic);
end jkffbeh;
architecture jkffbehar of jkffbeh is
signal jk : std_logic_vector (1 downto 0);
begin
jk <= j&k;
process (cp,j,k)
begin
if(cp’event and cp=’1′)then — positive edge trigger
case jk is
when “00”=>q<=q;
when “01”=>q<=’0′;
when “10”=>q<=’1′;
when “11”=>q<= not q;
when others => q <= q;
end case;
end if;
end process;
end jkffbehar;
VHDL Code For D-FF Behavioral Model
VHDL Code For D-FF Behavioral Model
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dffbeh is
Port ( d,clk : in STD_LOGIC;
q,qb : inout STD_LOGIC);
end dffbeh;
architecture dffbehar of dffbeh is
begin
process(d,clk)
begin
if(clk’event and clk=’1′) then q<=d; qb<=not d;
end if;
end process;
end dffbehar;
VHDL Code For D-FF Structural Model
VHDL Code For D-FF Structural Model
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dffst is
Port ( d,clk : in STD_LOGIC;
q,qb : inout STD_LOGIC);
end dffst;
architecture dffstar of dffst is
component nand21
port(a,b: in STD_LOGIC;
y:out STD_LOGIC);
end component;
signal d1,s1,r1:STD_LOGIC;
begin
n0: nand21 port map(d,clk,s1);
n1: nand21 port map(d,d,d1);
n2: nand21 port map(d1,clk,r1);
n3: nand21 port map(s1,qb,q);
n4: nand21 port map(r1,q,qb);
end dffstar;
— nand gate
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity nand21 is
Port ( a,b : in STD_LOGIC;
y : out STD_LOGIC);
end nand21;
architecture Behavioral of nand21 is
begin
y <= a nand b;
end Behavioral;
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