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vhdl
sr flip flop
SR-FF Data Flow Model
VHDL Code For SR-FF Behavioral Model
Up-Down Counter
T-FF
ALU
D flip flop
D-FF Behavioral Model
D-FF Data Flow Model
Down-Counter
JK-FF
SHIFT REGISTER (Serial In Parallel Out)
SHIFT REGISTER (Serial In Serial Out)
SHIFT REGISTER Parallel In Parallel Out
Up-Counter
verilog coding
BASIC CODES
verilog code for two input logic gates and test bench
logic gates
LEDs and switches
adders
verilog code for Half Adder and testbench
verilog code for adder and test bench
verilog code for Full adder and test bench
verilog code for carry look ahead adder
Study of synthesis tool using fulladder
8-bit adder/subtractor
verilog code for 8 bit ripple carry adder and testbench
subtractor
verilog code for full subractor and testbench
verilog code for half subractor and test bench
flip flops
Verilog Code for SR-FF Data flow level:
Verilog Code for SR-FF Gate level
verilog code for D latch and testbench
Verilog Code for D-FF Behavioral level
verilog code for D latch and testbench
Verilog Code for JK-FF Gate level:
verilog code for D flipflop and testbench
ALU
Verilog code for ALU using Functions
verilog code for ALU with 8 Operations
Verilog code for ALU (16 Operations )
DESIGN AND IMPLEMENTATION OF ALU USING FPGA SPARTAN 2
REGISTERS
verilog code for 4-bit Shift Register
Verilog code for 8bit shift register
Verilog code for Generic N-bit Shift Register
verilog code for SIPO and Testbench
verilog code for SISO and testbench
verilog code for PIPO and Testbench
Verilog Code for Parallel In Parallel Out
COUNTERS
verilog code for ASYNCHRONOUS COUNTER and Testbench
verilog codes for upcounter and testbench
verilog code for downcounter and testbench
Verilog code BCD counter
FSM OF UP/DOWN COUNTER
verilog code for updowncounter and testbench
Verilog Code for Ripple Counter
MUX AND CODERS
verilog code for encoder and testbench
verilog code for decoder and testbench
verilog code for 4 bit mux and test bench
COMPARATORS
Verilog code for 2-bit Magnitude Comparator
Verilog code for 4bit comparator
verilog code for 4-bit magnitude comparator
MOORE AND MEALAY
verilog code for Mealy Machine
verilog code for Moore Machine
MULTIPLIERS
verilog code for multiplier and testbench
verilog code for multiplier and testbench
8 x 8 multiplier using ADD/SHIFT method
verilog code for Accumulator and testbench
REAL TIME CLOCK
Traffic Light Controller Interface
MEMORY
SRAM with Memory size is 4096 words of 8 bits each
Verilog code for RAM and Testbench
verilog code for RAM with 12-bit Address lines
CONVERTERS
verilog codes for Gray to Binary Converter
List of companys
VLSI companies in world wide
c program
MODELING OF P Channel MOSFET USING C
N Channel MOSFET Modeling
C program read ten values to an array variable and to locate and display value using pointers
convert the string in uppercase to lowercase and vice versa
calculate total marks using array of structures
calculate Sum of all individual digits and also print the above number in reverse order
C program to Reverse (i) String (ii) N integer numbers stored in any array using pointers
calculate sum and average of given three numbers
c program to remove the substring from the given string
C program to read ten values to an array variable and to locate and display value using pointers
c program to find the length of the string using pointers
C program to find the factorial of a given number (i) Without recursion(ii) With recursion
C program to print the string arguments in reverse order using command line arguments
C program to copy one file into another
c program to find PALINDROME or not
c program to find the address of a variable
Embedded systems
PARTITION BETWEEN FPGA AND ARM ON PERFORMANCE CHARACTERISTICS
APPLICATION DEVELOPMENT & HARDWARE AND SOFTWARE PARTITIONING
BUZZER
DIP SWITCH
KEYPAD
RELAY
LED
SEVEN SEGMENT
Implementation of Wireless Communication Protocol on an Embedded System (RFID)
OPEN SOURCE SOFTWARE PROGRAMMING (LINUX) USING ARM9 PROCESSOR TO DISPLAY A MESSAGE
ME VLSI DESIGN LAB2
MODEL TRAIN CONTROLLER
ALARM CLOCK CONTROLLER
8 BIT ALU(vhdl)
FREQUENCY DIVIDER USING PLL(vhdl)
4 BIT SLICED PROCESSOR (vhdl)
IMPLEMENTATION OF ELEVATOR CONTROLLER
Microprocessor and Controllers
16-BIT ADDITION OF TWO NUMBERS
16-BIT SUBTRACTION
8 x 8 multiplier using ADD/SHIFT method
8-bit adder/subtractor
8-BIT ADDITION OF TWO NUMBERS
8-BIT SUBTACTION OF TWO NUMBERS
8085
ARRANGING DATA BYTES IN DESCENDING ORDER
Ascending Order
DIVISION OF 8-BIT DATA
Largest Element In an Array
ALGORITHM
AVL TREE
BACKTRACKING ALGORITHM – KNAPSACK PROBLEM
BINARY SEARCH TREE
BINARY TREE TRAVERSALS
BRANCH AND BOUND ALGORITHM FOR TRAVELLING SALESPERSON PROBLEM
CIRCULAR QUEUE TO SIMULATE A PRODUCER-CONSUMER PROBLEM
DIJKSTRA’S ALGORITHM
DOUBLE LINKED LIST
HASHING TECHNIQUES
PRIMS ALGORITHM
QUEUE USING BINARY HEAPING
POLYNOMIAL ADDITIONS
SINGLY LINKED LIST
TOPOLOGICAL SORTING
VLSI QUESTION AND ANSWER
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