verilog code for ASYNCHRONOUS COUNTER and Testbench

ASYNCHRONOUS COUNTER

module asynchronouscountermod(clk, clear, q);

input clk;

input clear;

output [3:0] q;

reg [3:0] q;

 

always @(negedge clk or posedge clear)

q[0]<=~q[0];

always @(negedge q[0] or posedge clear)

q[1]<=~q[1];

always @(negedge q[1] or posedge clear)

q[2]<=~q[2];

always @(negedge q[2] or posedge clear)

begin

if(clear)

q <=4’b0000;

else

q[3]<=~q[3];

end

endmodule

 

 

TEST BENCH

module asynchronouscountert_b;

reg clk;

reg clear;

wire [3:0] q;

asynchronouscountermod uut (.clk(clk),.clear(clear),.q(q) );

initial begin

clk = 0;

clear = 0;

#5 clear=1’b1;

#5 clear=1’b0;

end

always #5 clk=~clk;

initial #200 $stop;

endmodule