verilog code for RAM with 12-bit Address lines

module rammod(addr,w,addw);

input [12:0]addr,addw;

input [15:0]w;

reg [15:0]x[2047:0];

reg [15:0]y;

always @(addw or w)

begin

if(addw>0 &&addw<2047)

x[addw]=w;

else

$display(“invalid address”);

end

always @(addr)

begin

if(addr>0 && addr<2047)

y=x[addr];

else

$display(“invalid address”);

end

 

endmodule

Verilog code for RAM and Testbench

RAM

 

module rammod (clk, we, addr, din, dout);

input clk;

input we;

input [4:0] addr;

input [3:0] din;

output [3:0] dout;

reg [3:0] ram [31:0];

reg [3:0] dout;

always @(clk)

begin

if (we)

ram[addr] <= din;

else

dout <= ram[addr];

end

endmodule

 

TEST BENCH

module ramt_b;

reg clk;

reg we;

reg [4:0] addr;

reg [3:0] din;

wire [3:0] dout;

rammod uut ( .clk(clk),.we(we),.addr(addr),.din(din), .dout(dout) );

initial begin

clk = 0;

we = 0;

addr = 0;

din = 0;

#10 we=1’b1;

#10 addr=5’b00001;din=4’b0001;

#10 addr=5’b00010;din=4’b0010;

#10 addr=5’b00011;din=4’b0011;

#10 addr=5’b00100;din=4’b0100;

#10 addr=5’b00101;din=4’b0101;

#10 addr=5’bxxxxx;din=4’bxxxx;

#10 we=1’b0;

#10 addr=5’b00001;

#10 addr=5’b00010;

#10 addr=5’b00011;

#10 addr=5’b00100;

#10 addr=5’b00101;

end

always #10 clk = ~clk;

initial #150 $stop;

endmodule