verilog code for SISO and testbench

SISO

module sisomod(clk,clear,si,so);

input clk,si,clear;

output so;

reg so;

reg [3:0] tmp;

always @(posedge clk )

begin

if (clear)

tmp <= 4′b0000;

else

tmp <= tmp << 1;

tmp[0] <= si;

so = tmp[3];

end

endmodule

TEST BENCH

module sisot_b;

reg clk;

reg clear;

reg si;

wire so;

sisomod uut (.clk(clk), .clear(clear),.si(si),.so(so));

initial begin

clk = 0;

clear = 0;

si = 0;

#5 clear=1′b1;

#5 clear=1′b0;

#10 si=1′b1;

#10 si=1′b0;

#10 si=1′b0;

#10 si=1′b1;

#10 si=1′b0;

#10 si=1′bx;

end

always #5 clk = ~clk;

initial #150 $stop;

endmodule