verilog code for Full adder and test bench

FULL ADDER

Module

module fa(a, b, c, sum, carry);

input a;

input b;

input c;

output sum;

output carry;

wire d,e,f;

xor(sum,a,b,c);

and(d,a,b);

and(e,b,c);

and(f,a,c);

or(carry,d,e,f);

endmodule

TEST BENCH

module fulladdt_b;

reg a;

reg b;

reg c;

wire sum;

wire carry;

fa uut (  .a(a),   .b(b),.c(c),.sum(sum),.carry(carry)  );

initial begin

#10 a=1’b0;b=1’b0;c=1’b0;

#10 a=1’b0;b=1’b0;c=1’b1;

#10 a=1’b0;b=1’b1;c=1’b0;

#10 a=1’b0;b=1’b1;c=1’b1;

#10 a=1’b1;b=1’b0;c=1’b0;

#10 a=1’b1;b=1’b0;c=1’b1;

#10 a=1’b1;b=1’b1;c=1’b0;

#10 a=1’b1;b=1’b1;c=1’b1;

#10$stop;

end

endmodule