verilog code for decoder and testbench

DECODER

 

module decodermod(e, a, b, d);

input e;

input a;

input b;

output [7:0] d;

assign d[0]=(~e)&(~a)&(~b);

assign d[1]=(~e)&(~a)&(b);

assign d[2]=(~e)&(a)&(~b);

assign d[3]=(~e)&(a)&(b);

assign d[4]=(e)&(~a)&(~b);

assign d[5]=(e)&(~a)&(b);

assign d[6]=(e)&(a)&(~b);

assign d[7]=(e)&(a)&(b);

endmodule

TEST BENCH

module decodert_b;

reg e;

reg a;

reg b;

wire [7:0] d;

decodermod uut ( .e(e),.a(a),.b(b),.d(d) );

initial begin

#10 e=1′b0;a=1′b0;b=1′b0;

#10 e=1′b0;a=1′b0;b=1′b1;

#10 e=1′b0;a=1′b1;b=1′b0;

#10 e=1′b0;a=1′b1;b=1′b1;

#10 e=1′b1;a=1′b0;b=1′b0;

#10 e=1′b1;a=1′b0;b=1′b1;

#10 e=1′b1;a=1′b1;b=1′b0;

#10 e=1′b1;a=1′b1;b=1′b1;

#10$stop;

end

endmodule