verilog code for D flipflop and testbench

D FLIPFLOP

module dflipflopmod(q, d, clk);

output q;

input d;

input clk;

reg q;

always @(posedge clk)

q=d;

endmodule

 

TEST BENCH

 

module dflipflopt_b;

reg d;

reg clk;

wire q;

dflipflopmod uut (.q(q),.d(d), .clk(clk) );

initial begin

// Initialize Inputs

d = 0;

clk = 0;

end

always #3 clk=~clk;

always #5 d=~d;

initial                     #100 $stop;

endmodule