IMPLEMENTATION OF 8 BIT ALU(vhdl)

AIM:
To design and implement the 8 bit ALU in FPGA / CPLD
HARDWARE REQUIRED:

Spartan 3E FPGA
Cool runner 2 CPLD

SOFTWARE REQUIRED:

Xilinx 9.1 ISE

THEORY:
In computing, an arithmetic logic unit (ALU) is a digital circuit that performs arithmetic and logical operations. The ALU is a fundamental building block of the central processing unit of a computer, and even the simplest microprocessors contain one for the purposes such as maintaining timers. The processors found inside modern CPUs and graphics processing units (GPUs) accommodate very powerful and very complex ALUs; a single component may contain a number of ALUs. Most ALUs can perform the following operations:
 Bitwise logic operations (AND, NOT, OR, XOR)
 Integer arithmetic operations (addition, subtraction, multiplication and division)
 Bit-shifting operations (shifting or rotating a word by a specified number of bits to the left or right, with or without sign extension). Shifts can be seen as multiplications and divisions by a power of two.

The inputs to the ALU are the data to be operated on (called operands) and a code from the control unit indicating which operation to perform. Its output is the result of the computation.
Some of the arithmetic functions like addition, subtraction, multiplication and division and some logic functions like AND, OR, XOR and NOT are performed here in the program. The arithmetic and logic unit gets the input data from the input ports, maybe 4 to 32 bits depending on the application and operation and display the output via the output ports on the LED.

BLOCK DIAGRAM:

alu1

PROCEDURE:
Step 1: Define the inputs and outputs.
Step 2: Define wires if required.
Step 3: Declare a ‘case’ statement and inside the case define all the required operations under each case. Choosing a specific case, is based on the select input.
Step 4: When a particular case is chosen, only that operation is performed and the output is displayed.
Step 5: To continue the process for all the cases for a given input, use test bench and define particular period for each case.

PROGRAM:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity alu is
port( clk : in std_logic;
a : in std_logic_vector(3 downto 0);
b : in std_logic_vector(3 downto 0);
sig : in std_logic_vector(3 downto 0);
c : out std_logic_vector(7 downto 0);
carry : out std_logic);
end alu;
architecture Behavioral of alu is
signal reg1,reg2 : integer;
signal tmp : std_logic_vector(8 downto 0);
signal delay : std_logic_vector(2 downto 0):= “000″;
begin
process(a,b,sig)
variable cnt :integer range 0 to 16 := 0;
begin
if rising_edge(clk) then
c <= "00000000";
carry –addition
tmp(4 downto 0) <= conv_std_logic_vector((conv_integer(a) + conv_integer(b)),5);
c(3 downto 0) <= tmp(3 downto 0);
carry –subtraction tmp(4 downto 0) <= conv_std_logic_vector((conv_integer(a) – conv_integer(b)),5);
c(3 downto 0) <= tmp(3 downto 0);
carry –Multiplication
c –Division
c(3 downto 0)
reg1 <= conv_integer(a);
reg2 <= conv_integer(b);
delay
if(reg2 = 0) then
delay <= "011";
else
delay
if(reg1 >=reg2) then reg1 <= reg1-reg2; cnt:=cnt + 1; delay <= "010";
else
tmp(3 downto 0) <= conv_std_logic_vector(cnt,4);
delay tmp(3 downto 0) <= "0000";
delay cnt := 0;
delay
end case;
when “0100″ => – and gate
c(3 downto 0) – or gate
c(3 downto 0) — xor gate
c(3 downto 0) – nand gate
c(3 downto 0) – nor gate
c(3 downto 0) — xnor gate
c(3 downto 0)<= a(3 downto 0) xnor b(3 downto 0);
when "1010" =
c(3 downto 0)
end case;
end if;
end process;
end Behavioral;

UCF FILE :
#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
NET “a” LOC = “p5″ ;
NET “a” LOC = “p4″ ;
NET “a” LOC = “p3″ ;
NET “a” LOC = “p2″ ;
NET “b” LOC = “p9″ ;
NET “b” LOC = “p8″ ;
NET “b” LOC = “p7″ ;
NET “b” LOC = “p6″ ;
NET “c” LOC = “p29″ ;
NET “c” LOC = “p28″ ;
NET “c” LOC = “p27″ ;
NET “c” LOC = “p25″ ;
NET “c” LOC = “p23″ ;
NET “c” LOC = “p22″ ;
NET “c” LOC = “p21″ ;
NET “c” LOC = “p20″ ;
NET “carry” LOC = “p38″ ;
NET “clk” LOC = “p44″ ;
NET “sig” LOC = “p15″ ;
NET “sig” LOC = “p14″ ;
NET “sig” LOC = “p12″ ;
NET “sig” LOC = “p10″ ;
#PACE: Start of PACE Area Constraints
#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PACE

OUTPUT WINDOW :
alu2

DEVICE CONFIGURATION :-
SPARTAN 3E :-

alu3

Family – Spartan 3E
Device – XC3S500E
Package – FT256
Speed – - 4

COOL RUNNER 2 CPLD :-

alu4

Family _ Cool runner 2 CPLD
Device – XC2C256
Package – PQ208
Speed – - 7

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