SHIFT REGISTER (Serial In Serial Out)

SHIFT  REGISTER (Serial In Serial Out)

 

VHDL Code For SISO

 

library ieee;

use ieee.std_logic_1164.all;

entity siso is

port(din,clk:in std_logic;

dout:out std_logic);

end siso;

architecture sisoarc of siso is

signal sr_bit: std_logic_vector(3 downto 0):=”0000″;

begin

process(clk)

begin

if (clk=’1′)then

dout <= sr_bit(0);

sr_bit <= din & sr_bit(3 downto 1);

end if;

end process;

end sisoarc;

About these ads

Leave a Reply

Fill in your details below or click an icon to log in:

WordPress.com Logo

You are commenting using your WordPress.com account. Log Out / Change )

Twitter picture

You are commenting using your Twitter account. Log Out / Change )

Facebook photo

You are commenting using your Facebook account. Log Out / Change )

Google+ photo

You are commenting using your Google+ account. Log Out / Change )

Connecting to %s