SHIFT REGISTER (Serial In Parallel Out)

SHIFT  REGISTER (Serial In Parallel Out)

 

VHDL Code For SIPO

 

library ieee;

use ieee.std_logic_1164.all;

entity sipo is

port(din,clk:in std_logic;

dout:out std_logic_vector(3 downto 0));

end sipo;

architecture sipoarc of sipo is

signal sr_bit: std_logic_vector(3 downto 0):=”0000″;

begin

process(clk)

begin

if (clk=’1′)then

sr_bit <= din & sr_bit(3 downto 1);

end if;

end process;

process(sr_bit)

begin

dout <= sr_bit;

end process;

end sipoarc;

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