SHIFT REGISTER (Parallel In Serial Out)

SHIFT  REGISTER (Parallel In Serial Out)

 

VHDL Code For PISO

 

library ieee;

use ieee.std_logic_1164.all;

entity piso is

port(din:in std_logic_vector(3 downto 0);

load_shtbar: in std_logic;

clk:in std_logic;

dout:out std_logic);

end piso;

architecture pisoarc of piso is

signal sr_bit: std_logic_vector(3 downto 0):=”0000″;

begin

process(clk)

begin

if (clk=’1′)then

if (load_shtbar=’1′)then

sr_bit <= din;

else

sr_bit <=’0’& sr_bit(3 downto 1);

end if;

dout <= sr_bit(0);

end if;

end process;

end pisoarc;

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